The present disclosure concerns digital communications systems and, more particularly, apparatus for synchronizing a bit clock in a digital receiver to be in phase with data bits of a received data stream.
In digital communication systems, a clock is often required at the digital data receiver to indicate the start and completion times of each data bit time interval. This clock must be of proper phase with respect to the received signal and is usually so phased by reference to a selected characteristic of the received signal itself. Typical systems using a powerline transmission medium are disclosed and claimed in U.S. Pat. No. 3,973,240, issued Aug. 3, 1976; U.S. Pat. No. 3,973,087, issued Aug. 3, 1976; U.S. Pat. No. 3,944,723, issued Mar. 16, 1976; U.S. Pat. No. 4,135,181, issued Jan. 16, 1979; and U.S. Pat. No. 4,161,720, issued July 17, 1979, all assigned to the assignee of the present application and all incorporated herein by reference in their entirety.
When the received signal is particularly rich in data transitions, one typical approach is to detect such data transitions and lock a phase-lock loop to the data transitions to achieve synchronism. It is not always possible to employ an optimum data detection scheme, whereby the input to a phase-locked loop will be relatively noisy and the loop may not achieve the desired synchronism with the incoming data bits stream. The deleterious effects of input noise may be reduced by increasing the phase-lock loop time constant, whereby many data cycles are averaged. Advantageously, as many data bit transitions as possible should occur in the data stream for a long-time-constant phase-locked loop to attain maximum advantage; systems utilizing such a synchronizing scheme will typically also utilize data coding schemes which deliberately introduce data transitions so that the maximum number of data transmissions occur for any bit stream.
However, in digital communication systems which transmit relatively long strings of data bits without transitions, and/or have a signal-to-noise ratio which is relatively low, the required phase-locked loop time constant would become so great that a loop many not be designable which will pull into phase-lock. Similarly, if relatively low frequencies are utilized, the required long time constants may become difficult, if not impossible, to physically realize. Thus, a means for phasing a local, or data bit, clock in a digital receiver to be in phase with the data bits of a received data stream, without requiring unusually long time constants, is desirable.